1. Field of the Invention
The present invention relates to a memory cell which is configured so as to select a write word line current driver circuit for data write operations or a ground for data read operations, a memory circuit block containing the memory cell, a data writing method, and a data reading method.
2. Description of Related Art
A memory cell 44 shown in FIG. 3 is a typical memory cell having one transistor and one magnetic tunnel junction (MTJ) which has been used in a 1-Kbit magnetic random access memory (MRAM) chip and 512-bit MRAM chip and is expected to be used in the future. In this memory cell 44, a nonvolatile MTJ element 38 is used as a memory element. In a memory cell array 43 of a typical memory circuit block 42 used in an MRAM or the like, word lines 50 and bit lines 46 are arranged in a matrix and the memory cells 44 are placed at the intersections of the word lines 50 and bit lines 46, as shown in FIG. 4.
The MTJ element 38 is a nonvolatile memory element composed of at least three layers of thin films: a pinned ferromagnetic layer 36 whose magnetization direction is fixed, a tunnel barrier 34 which drives a tunneling current, and a free ferromagnetic layer 32 which can change the direction of magnetization. The positions of the free layer 32 and the pinned layer 36 can be reversed, and therefore the pinned layer 36 can be connected to the bit line 46. When the direction of magnetization of the free layer 32 is the same as that of the pinned layer 36, the data stored in the MTJ element 38 is “0”. When the direction of magnetization of the free layer 32 is different from that of the pinned layer 36, the data stored in the MTJ element 38 is “1”. The bit line 46 is used for reading and writing data stored in the MTJ element 38.
In FIG. 3, a first conductive structure 48 electrically connects the MTJ element 38 to a diffusion area n of a drain (D) of a metal oxide semiconductor field effect transistor (MOSFET) 20 formed on a semiconductor substrate. The first conductive structure 48 is composed of MX, V2, M2, V1, M1, and CA wherein MX, M1, and M2 each are a metal line layer and V1, V2, and CA each are a conductor embedded in a via hole in an insulating layer.
A gate of the MOSFET 20 is part of a read word line 18. In a read operation, the MOSFET 20 is turned on by applying a read voltage to the word line 18, and thereby a current path from the bit line 46 to a ground 28 is formed. The resistance across the MTJ element 38 depends on the direction of magnetization of the free ferromagnetic layer 32 relative to that of the pinned ferromagnetic layer 36. Thus, the data stored in the MTJ element 38 can be read out as a current flowing through the MTJ element 38 or as a voltage value obtained from the current and the resistance of the MTJ element 38.
In a write operation, write currents flow both along the write word line 50 and along the bit line 46, thereby generating a combined magnetic field. The combined magnetic field can switch the direction of the magnetization of the free ferromagnetic layer 32. The direction of the magnetization of the free layer 32 is determined by the direction of the write current along the bit line 46.
In the known memory cell 44 shown in FIG. 3, an M1 layer 52 is used as a metal layer for the connection to the ground in a read operation, and an M2 layer is used for the write word line 50. Therefore, a current drives from the MTJ element 38 to the diffusion area n of the MOSFET 20 must go through the MX, V2, M2, V1, M1, and CA. Since many layers are required in the memory cell 44, yields are reduced in the production process and the reliability of a resulting product is decreased. In addition, the formation of many layers causes an increase in production cost. In such applications as a system-on-chip which incorporate an MRAM and other circuits on a single chip, global wiring is required for connection among circuit blocks on the chip. In those cases, if wiring layers are used up in the MRAM, additional upper wiring layers are required for global wiring and power supply wiring.
An object of the present invention is to provide a memory cell, a memory circuit block, a data writing method, and a data reading method which realize a high-yield, high-performance, low-power, high-reliability, and low-cost semiconductor magnetic memory and large scale integration (LSI) having the reduced number of metal line layers.